1. Field of the Invention
The present invention relates to semiconductor technology and, in particular, relates to fabrication processes for conductive layers on substrates.
2. Description of the Related Art
Conventional fabrication of conductive structures, such as patterned interconnects, typically involves forming recesses, trenches, or vias in or on a substrate, and then filling or overfilling these features with various conductive materials, such as copper, poly-silicon, metal, or various metal alloys. Sometimes excessive conductive material, such as overfill or overburden, is removed by planarization using, for example, chemical mechanical polishing or the like to thereby form isolated conductive structures, such as traces, vias, wires, and/or wire bonding pads. Such metalization processes can sometimes avoid photolithographic mask and etching processing of conventional metal line definition.
In one such process, recessed features, such as trenches, vias, and wire bonding pads, are formed in an insulating substrate, such as an interlayer dielectric (ILD) layer, using reactive ion etching (RIE). In addition, electrochemical deposition (ECD) is sometimes used to deposit copper or various other conductive materials to a sufficient thickness to fill these features so as to form the desired conductive structures. In certain circumstances, a seed layer can first be deposited as part of the deposition process. In other circumstances, the deposition of copper material is preceded by the deposition of a thin barrier layer, which inhibits diffusion of copper into the underlying substrate or ILD layer. Moreover, the copper deposition is typically followed by annealing the copper by heating the wafer to a temperature between approximately 100° and 500° C. (e.g., 200° C.).
Unfortunately, defects can be introduced at various stages of processing (e.g., RIE, seed/barrier deposition, ECD, and CMP). In many cases, some of these defects can be removed with annealing processes. However, the excessive overburden of copper material above the conductive structures can create stresses during the annealing process, which can cause a multitude of defects and adversely impact the electrical characteristics of the copper material. For example, stresses created by the thermal cycling of heating and cooling during annealing can cause the copper material to lift off from a portion of the recessed trench or via, thereby creating voids, which can inhibit the conductive properties of the copper material.
In addition, conductive structures are typically formed in or on a substrate, including ILD layers, at various widths or pitches, wherein a via, for example, can be classified as a “smaller” recessed feature and a wire bonding pad, for example, can be classified as a relatively “larger” recessed feature. In general, conventional metalization techniques deposit or form a single layer of copper material on the substrate so as to simultaneously fill the “smaller” and “larger” recessed features, which results in excessive overfill or overburden of copper material above the “smaller” recessed feature or via.
Moreover, subsequent annealing of the copper layer can cause the copper material to flow at elevated temperatures. In general, the coefficient of thermal expansion (CTE) for copper is typically greater than the CTE for substrate materials including ILD layers. Thus, during annealing, copper material expands more than the substrate material at elevated temperatures. Unfortunately, the expansion forces of the copper and substrate material can cause copper to flow out of the “smaller” features. Typically, excessive overburden or thickness of copper material results in increased expansive stresses. Once cooled, the copper and substrate materials contract. In general, copper contracts more than the substrate due to the difference in the CTE. Therefore, the copper can shrink in the “smaller” features and the overburden can contract as well such that an excessive overburden of copper above the “smaller” features results in a larger contracting volume, which results in larger contracting forces pulling the copper out of the “smaller” features.
The contraction or shrinkage of the overburdened copper layer can cause the copper material to lift off from portions of the “smaller” recessed feature or via, thereby creating a void between the copper layer and portions of the “smaller” recessed feature. Therefore, there currently exists a need to improve the processing techniques associated with forming conductive structures so as to improve the physical and electrical characteristics thereof.